| VLSI Designs: Verification |
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| FPGA: Test Bench &
VDL |
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Verilog, VHDL, Vera,
E, PSL, SystemVerilog |
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Prototypes &
Validations |
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| ASIC: High-level and
BFM Models |
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SystemC Models |
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| Test Bench & VDL |
| Protocol, Assertion
or Property based |
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eVC, PC, OVA or AIP,
VIP |
| Formal & Hybrid
Formal |
| Post Layout |
| SOC: System
Level Verification |
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| Testing Methodolgies |
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OVM, VMM, ERM/URM Compliant Verification Models |
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OS Support:
 
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Click here to contact Silicon
Interfaces for VLSI Design Services.
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Cadence Incisive Enterprise Simulator 8.1 |
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QuestaSim 6.4 b |
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Synopsys VCS Mx 2009.12 and VERA |
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Specman Elite |
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Magellan |
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Debussy (Novas), Vnavigator Transeda) STM proprietary C Language assembler/compiler
toolsets |
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Hardware Accelerator Platforms (AXIS) |
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OVM compliant Gigabit Ethernet MAC System Verilog VIP |
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OVM compliant IEEE 1394 (Firewire Link Layer Controller) SystemVerilog VIP. |
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VMM based USB 2.0 Function Controller SystemVerilog VIP |
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VCS-MX
Interface with third party E tool |
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ERM/URM Compliant 1394 e/uVC |
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USB OVA
AIP |
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RapidIO
VIP |
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OpenVera
RVM VIP |
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Corporate
Application Engineering for VCS, IPX and Covermeter for Synopsys |
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Verification
of Level 3 Mapper SDH/SONET Device |
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Verification
of SAN Controller ASIC |
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Verification
of Mainstream H263/MPEG Video Codec |
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