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| VLSI Design Services |
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| The purpose of this group is to be
full-fledged design center for design and verification as well as customer and
product support for EDA Companies. |
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| MODELING: |
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Language and HDL-based modeling & synthesis of libraries, components, ASICs & boards. |
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| DESIGN: |
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The activities include schematic design of ASICs in CMOS and other technology using standard cell, gate arrays and FPGA methodology, test vector generation and minimization, simulation and testing. |
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| The design services include: |
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Design services for ASIC/FPGA in Verilog/VHDL by top down methodology |
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Verification and testing services using Verilog/VHDL/Vera/E Language |
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Development of eVC using E Language |
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Development of VIP using VERA |
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Development of Assertion based Verification IP using OVA |
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Development of ReUsable Verification Blocks |
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Analog and Mixed Signal Designs |
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| Modeling Languages used are: |
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Verilog & VHDL |
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SystemC |
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C/C++ |
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System Verilog |
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| Verification Languages used are: |
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E Language for Verification |
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Vera for Verification |
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Sugar |
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| Domain Knowledge: |
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Silicon Interfaces offers Designs
Services in the areas of Networking, Data Communications, Interconnect and
Storage, primarily in the areas of System Verilog/Verilog/VHDL for Design,
Modeling and Verification of complex SoC, ASIC and FPGAs. We have a long
history of Design Services, now 10 years in the Silicon Valley and 5+ years in
Europe as well as 1+ Years in Japan. Apart from front-end we also do work on
Mixed-Mode, Analog and IC backend through our Associate companies and we offer
a complete solution to our Customer. An interesting aspect of our Design
Services is that we undertake work in our state-of-the-art Design Centers based
in Mumbai with tools from top leading EDA Companies. We also provide
specialized Verifications, VHDL to Verilog Translation, Libraries and IP Cores
Development and EDA Product Support Services.
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Silicon Interfaces has been working
in various target domain areas over the years based on specific market needs
and has operated in Networking, Data Communications, Interconnect,
Microcontrollers, Graphics, DSP and other areas.
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| Currently the focus is on: |
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Networking |
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Wireless – Bluetooth
BaseBand, 802.11 a+b, Cable - Gigabit Ethernet MAC & 7990, Optical – SONET
STS-1/3 Framer |
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Data Communications |
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USB2.0, 1394, 8530, UART |
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Interconnect |
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RapidIO, InfiniBand LPE |
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Microcontrollers |
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8051 |
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| Software Drivers and Firmware for some of the IPs, namely: |
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Gigabit Ethernet MAC Controller |
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Bluetooth |
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1394 |
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802.11 a+b (Under development) |
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Methodologies and
Standards:
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VLSI design methodology |
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Modeling methodology |
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VHDL/Verilog modeling standard |
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Verification methodologies |
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Silicon Interfaces is
under process of implementing ISO-9001 : 2000
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| Verification Methodology: |
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Develop and model test plan |
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Develop and model test benches |
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Run automated scripts for test plan/test bench |
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If existing core, capture signals by logic analyzer on existing systems and convert them to test vectors |
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After prototype is done, run test vectors on prototype running on a daughter board |
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| Project Methodology: |
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Proposal |
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Specifications |
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Project Management - Strategy |
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Configuration & Change Order Management |
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Quality Assurance and Risk Management - Strategy |
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Detail Design |
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Implementation – Coding & Integration |
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Verification and Testing |
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Release |
| IC Services for Front-end, Analog, Mixed Mode and RF: |
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Layout |
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Design Rule Check |
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Simulation and Timing Verification post layout and provide SDF files |
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GDS II |
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Interface with foundries |
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Packaging |
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| Tools Experience: |
| Front-End Tools: |
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Entry |
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Vim Editor, Xemacs |
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Simulation |
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Mentor Modelsim VSim, Synopsys
VCSi-Verilog, Scirocco-VHDL, Cadence NC-Sim mixed-language. |
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Synthesis |
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Exemplar Galileo and Leonardo
Specrum, Synopsys design & test compiler. |
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Verification |
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Specman Elite, Vera, Cadence
Verification Cockpit. |
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FPGA |
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Xilinx, Altera, Actel, etc. |
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Library dev |
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Dragster vital compliant. |
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Translators |
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Avant! InterHDL V2VL. |
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Version Control |
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CVS |
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| Analog Tools: |
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Environment |
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Analog Artist (Cadence) |
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Schematic Entry |
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Composer (Cadence) |
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Simulation |
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HSPICE, Spectre (Cadence) |
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| Back-End Tools: |
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Virtuoso -XL Layout Editor |
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CHIP ASSEMBLY ROUTER |
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Diva DRC/LVS |
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| Projects Undertaken: |
| Onsite: |
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Gigabit Development Kit ASIC design/ testing for Xaqti Corp, USA |
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Incorporating Multiple Operating System platform for Sun Workstations undertaken at Sun Microsystems - USA. 1.5 million gates. |
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Design & test of part of a Multimedia ASIC for Shareware Inc - USA. Subsidiary of Intel & Microsoft |
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Product support for Synopsys/Cadence - USA. |
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Design support for Toshiba – USA |
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Development Wireless LAN Adapter for PDA, Japan |
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Designing the Advanced Sonet E3/DS3 Receiver/Transmitter (DART) Device |
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Development of Multi-Codec Pipeline |
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Design Of Firmware To Activate the Front Panel Logic for Set-top Box of a Cable Modem for HP |
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Porting MVP (Multi-Media Video Processor) Debugger from Unix to NT. |
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Parallel debugger manager (PDM) to control debuggers for the processors on the MVP Chip |
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Design & Testing of the Networking Board for the Gigabit Ethernet Controller for Xaqti Inc - USA. |
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Verification of Level 3 Mapper SDH/Sonet Device |
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Development of Automative Embedded Controllers. |
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Testing VLSI Chips for Various Customers. |
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Macro Cell Designs for Customers Like Philips - USA. |
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Design of RF Interface for Barney Toy for Microsoft. |
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Verification of SAN Controller ASIC |
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Design and Development of dNTSC Receiver |
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Verification of Mainstream - H263/MPEG4 Video Codec, UK |
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Design, testing & synthesis of the receive FIFO of Agni |
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Corporate Applications Engineer for VCS, IPX and Covermeter for Synopsys |
| Offshore: |
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EtherSwitch (100Mb/s) ES100: Specification, Architecture and Validation |
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Two Port Ethernet-based Switch device. |
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LAN Analyzer VHDL Model. |
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Validation of Distributed Networking board. |
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FPGA (Actel, Xilinx) library development. |
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VHDL/Verilog libraries for foundries like SMOS, LSI, NCR, etc. |
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Wireless LAN Adapter. |
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Cable modem chip for Setup Box |
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Conversion of Agni and XMAC2 from VHDL to Verilog |
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Porting of TPC-10 Libraries to Synopsys EDA/Synthesis Tools |
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eSOC (Extensible System on a Chip) Design and Development |
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| IP Cores Developed by Silicon Interfaces: |
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RapidIO – Physical Layer Interfaces Core (also VIP, OVA, eVC) |
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USB2.0 – Function Controller (also OVA, eVC) |
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InfiniBand – Link Protocol Engine (also eVC) |
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Bluetooth BaseBand Controller (AMBA Interfaces, also OVA) |
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Gigabit Ethernet MAC |
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802.11 a+b – Wireless LAN |
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SONET – STS-1/3 Framer |
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7990 |
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1384 – Link Layer Controller |
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8530 – Serial Communication Controller |
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UART – Universal Asynchronous Receiver/Transmitter Core |
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8051 - Microcontroller |
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Our VLSI Symphony |
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Click here to contact Silicon Interfaces for VLSI Design Services.
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