As a recognized guru in the space of Verification Methodologies, Silicon Interfaces is a company which is the one stop solution for Verification in terms of coverage on Languages, Tools and Methodologies. Silicon Interfaces has the unique position to offer solutions in SystemVerilog based on Synopsys VMM, Mentor OVM/AVM and Cadence OVM/URM.

In addition to their portfolio IP's Silicon Interfaces has developed special verification IP's based on Assertion, Protocols and Property Checkers. We are leading providers of high-performance, productive, re-usable, industry standard Verification components using various VDL thereby optimizing cost and time to Market. These are separately sold outside the Portfolio and may be licensed for worldwide, networked licenses for unlimited use by a Member of the Silicon Cores Program.

Currently, the following have been released:

OVM-Compliant IEEE 1394 Link Layer Controller OVC is a fully documented, off-the-shelf component using the Open Verification Methodology for quickly enabling functional verification. The OVM based application programming interface (API) supports the IEEE standards of both SystemVerilog and e, enabling the powerful combination of field-proven verification capabilities, a multi-language interface, and scaleable OVM methodology.

Gigabit Ethernet Media Access Control (MAC) SystemVerilog OVC VIP is fully documented, off-the-shelf component for the developers of the Gigabit Ethernet MAC. Full Programmability and versatility of the OVC enables connection to any standard IEEE 802.3 based GEMAC device and supports application of Stimulus to the generic microcontroller Interface as well as PHY Interface.

Silicon Interfaces' USB 2.0 VMM SystemVerilog VIP is fully documented, off the shelf component for the verification of the USB 2.0 compliant Function Controller. USB 2.0 VMM VIP is developed using the Synopsys VMM methodology that is used in dynamic simulation of USB 2.0 based design. The VIP uses SystemVerilog to create comprehensive verification environments using coverage-driven, constrained-random and assertion-based techniques.

IEEE 1394a-2000 Link Layer Controller eVC is a fully documented, off the shelf component for Cadence Specman EliteTM functional verification environment.
The IEEE 1394 a-2000 link layer controller (from now on referred to only as 1394a) provides connectionless acknowledged data transfer services between a source node and destination node where node is an addressable device attached to the serial bus with at least a minimum set of control registers.

UART eVC is a fully documented, off the shelf component for Cadence Specman EliteTM functional verification environment. At the heart of every asynchronous serial system is the Universal Asynchronous Receiver/Transmitter (UART). The UART is responsible for implementing the asynchronous communication process as both a transmitter and a receiver (both encoding and decoding data frames). The UART not only controls the transfer of data, but the speed at which communication takes place.

USB 2.0 Function Controller Checker OVA IP is fully documented, off the shelf component for the Developers of the USB 2.0 compliant Function Controller. USB 2.0 OpenVera Assertions based Checker IP provides a concise, declarative mechanism to code the specification of sequences of events and activities of USB 2.0 Bus Protocol.
USB 2.0 OVA protocol rule Checker can work in a standalone mode i.e., can be plugged in any design verification environment, which uses the standard Protocol without disturbing the structure.

Silicon Interfaces’ USB 2.0 Vera RVM VIP is fully documented, off the shelf component for the Verification of the USB 2.0 compliant Function Controller.
USB 2.0 Vera RVM VIP can work in a standalone mode i.e. can be plugged with any Function Controller with standard pinouts without disturbing the structure.

Bluetooth 1.1 Baseband Controller Checker OVA IP is fully documented, off the shelf component for the Developers of the Bluetooth 1.1 Baseband Controller.
Bluetooth 1.1 Baseband controller Open Vera Assertions based Checker IP provides a concise, declarative mechanism to code the specification of sequences of events and activities of Bluetooth 1.1 Baseband controller Protocol.
Bluetooth 1.1 Baseband controller OVA protocol rule Checker can work in a standalone mode i.e., can be plugged in any design verification environment, which uses the standard Protocol without disturbing the structure.
Bluetooth 1.1 Baseband controller OVA AIP Checker is developed using the abstraction in OVA syntax that is used in dynamic simulation of Bluetooth 1.1 Baseband controller based design.