IPs

Silicon Interfaces is a powerhouse of Intellectual Property developed by its team of Engineers. These are owned and copyrighted by Silicon Interfaces and sold as Portfolio of IPs. Silicon Interfaces emerged out of “stealth mode” in the Development Phase effective January 16th, 2002 and unveiled a plethora of 12 IPs targeted for Networking (Wireless, Cable, Optical), Interconnect, Data Communication, Storage and Microcontroller.

Silicon Interfaces’ Bluetooth is a highly integrated Bluetooth BaseBand controller designed to form the heart of Bluetooth wireless communication systems.

Silicon Interfaces’ MAC core for Wireless LAN is compatible with 802.11 a b and g IEEE Standards. It is designed to handle packetized DSSS (Direct Sequence Spread Spectrum) and OFDM (Orthogonal Frequency Division Multiplexing) data transmissions; the software implementation supports all data rates. The MAC management or control functionality is implemented in firmware while the time critical functionality is implemented in hardware.

Silicon Interfaces’ MAC core for Wireless LAN is compatible with 802.11 a b and g IEEE Standards. It is designed to handle packetized DSSS transmissions; the software implementation supports all Data Rates. The MAC Management or Control Functionality is implemented in hardware.

Silicon Interfaces’ BBP core for Wireless LAN is compatible with 802.11 a b and g IEEE standards. It is designed to handle packetized DSSS (Direct Sequence Spread Spectrum) and OFDM (Orthogonal Frequency Division Multiplexing) data transmissions.

Silicon Interfaces Gigabit Ethernet Media Access Controller is highly integrated Gigabit Ethernet MAC solution for Gigabit applications. It simplifies design of Gigabit systems and reduces time-to-market. It is also a companion device for any Network Processor and enables glueless Gigabit Ethernet backbone connectivity.

The SI79C90 Local Area Network Controller for Ethernet is an IP core designed to greatly simplify interfacing a microcomputer or minicomputer to an IEEE 802.3/Ethernet Local Area Network.

Silicon Interfaces’ STS-1/3 Framer is a single core solution incorporating Synchronous Optical Network / Synchronous Digital Hierarchy (SONET / SDH) protocol as per ANSI and ITU standards. This significantly reduces the cost of implementing complex SONET / SDH System Designs.

Silicon Interfaces RapidIOTM is a packet-switched interconnect intended primarily as an intra-system interfaces for a chip-to-chip and board-to-board communications at Gigabyte-per-second performance levels. Developed as an open standard, the RapidIOä architecture addresses the needs of present and future systems. RapidIOä is focused as a processor, memory and memory mapped I/O interfaces optimized for use inside the chassis.

Silicon Interfaces’ USB2.0 function controller is a highly integrated USB solution for USB applications. It simplifies the design of the USB systems and reduces the time to market. The SI16USB20 is a USB Function controller core designed as per USB2.0 revision of USB standards. This core provides 480Mb/s high speed USB interface. It autonomously handles the USB transactions and data transfers, thus bridging the USB interface to an easy read/write parallel interface. It has the standard UTMI interface at host end and a generic microcontroller interface at the device end. It is a is single core solution incorporating USB2.0 protocol operating in Link Layer of Open System Interconnect (OSI) which significantly reduces the time and cost of implementing complex USB2.0 target system designs.

USB OTG Function Controller is a highly integrated USB OTG solution for USB OTG applications. SI22USBOTG11 is a USB OTG Function Controller Core designed as per USB OTG specification, which is a supplement to USB 2.0 specification. It has the standard UTM+ Interface at Host end and a generic Microcontroller Interface at the Device end. It is a single core solution, incorporating USB OTG operating in Link Layer of Open System Interconnect (OSI) which significantly reduces the time and cost of implementing complex USB OTG target system designs.

Silicon Interfaces’ Link core is a functional block available for insertion into a customer's ASIC design, which supports the IEEE 1394-1995 Draft specifications for a high-speed serial bus. The SI16FW10 Link core is implemented using VHDL synthesizable code to provide portability across Silicon Interfaces’ Gate Array and Cell-Based ASIC technologies.

The SI85SCC30 SCC is a dual channel, multiprotocol data communications peripheral. It supports virtually any serial data transfer application with important functions like baud rate generator, digital phase locked loop on the cell, it makes a self contained controller. In proportion to its functionalities the pin count is very less.

The SI40U550 IP core is a Universal Asynchronous Receiver Transmitter fully compatible with the de-facto standard 16550 UART.The SI40U550 core performs serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from the host . The host can read the UART status at any time. The SI40U550 core includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.

Silicon Interfaces’ Link Protocol Engine (LPE) is single core solution incorporating in Link Layer of Open System Interconnect (OSI) which significantly reduces the time and cost of implementing complex InfiniBand target system designs.

The SI80MC51 is an Intel microcontroller compatible, which is a true computer on chip. The Product incorporates all of the features found in a microprocessor CPU: ALU, Program Counter, Stack Pointer and Registers. It also has added the other features needed to make a complete computer: ROM, RAM, parallel I/O, serial I/O, counters, and a clock circuit.

This Program is available for Membership based on Annual Subscription. Membership Levels are based on Annual Subscription Fees and benefits (Status) range on Internal Usage of License for Usage and Geographical Locations. All currently available IPs are available to Members as well as all IP released in the year of Subscription as long as Fees are fully paid. Membership permits Members to guide the Program growth in terms of areas of development. Fees structures are based on three-Tiers, including Subscription, First Right of Call Charges and actual License Fees. First Right of Call permits the prospective Member Licensee to modify, add and re-target IPs to suit individual requirements and needs. License Fees vary based on Level of complexity and market factors for IPs.

To augment its Portfolio IPs for Function or Implementation IPs, the Silicon Cores program also has available special verification IPs based on Assertion, Protocols and Property Checkers. There are roll out plans for RVM-based VIPs as well as other Verification IPs. These are separately sold outside the Portfolio and may be licensed for worldwide, networked licenses for unlimited use by a Member of the Silicon Cores Program.

Currently, the following have been released:

IEEE 1394a-2000 Link Layer Controller eVC is a fully documented, off the shelf component for Cadence Specman EliteTM functional verification environment.
The IEEE 1394 a-2000 link layer controller (from now on referred to only as 1394a) provides connectionless acknowledged data transfer services between a source node and destination node where node is an addressable device attached to the serial bus with at least a minimum set of control registers.

UART eVC is a fully documented, off the shelf component for Cadence Specman EliteTM functional verification environment. At the heart of every asynchronous serial system is the Universal Asynchronous Receiver/Transmitter (UART). The UART is responsible for implementing the asynchronous communication process as both a transmitter and a receiver (both encoding and decoding data frames). The UART not only controls the transfer of data, but the speed at which communication takes place.

USB 2.0 Function Controller Checker OVA IP is fully documented, off the shelf component for the Developers of the USB 2.0 compliant Function Controller. USB 2.0 OpenVera Assertions based Checker IP provides a concise, declarative mechanism to code the specification of sequences of events and activities of USB 2.0 Bus Protocol.
USB 2.0 OVA protocol rule Checker can work in a standalone mode i.e., can be plugged in any design verification environment, which uses the standard Protocol without disturbing the structure.

Silicon Interfaces’ USB 2.0 Vera RVM VIP is fully documented, off the shelf component for the Verification of the USB 2.0 compliant Function Controller.
USB 2.0 Vera RVM VIP can work in a standalone mode i.e. can be plugged with any Function Controller with standard pinouts without disturbing the structure.

Bluetooth 1.1 Baseband Controller Checker OVA IP is fully documented, off the shelf component for the Developers of the Bluetooth 1.1 Baseband Controller.
Bluetooth 1.1 Baseband controller Open Vera Assertions based Checker IP provides a concise, declarative mechanism to code the specification of sequences of events and activities of Bluetooth 1.1 Baseband controller Protocol.
Bluetooth 1.1 Baseband controller OVA protocol rule Checker can work in a standalone mode i.e., can be plugged in any design verification environment, which uses the standard Protocol without disturbing the structure.
Bluetooth 1.1 Baseband controller OVA AIP Checker is developed using the abstraction in OVA syntax that is used in dynamic simulation of Bluetooth 1.1 Baseband controller based design.