Silicon Interfaces’ USB OTG Vera RVM VIP is fully documented, off the shelf component for the verification of the USB OTG Dual-Role Device.

This VIP is developed using the Synopsys’ OpenVera Reference Verification Methodology that is used in dynamic simulation of USB OTG based design.

Constrained random stimulus generation raises the abstraction level in test bench code.

DFV improves the observability of design errors by providing means for an abstract specification of the Device behavior using assertions.

Reusable test benches and reusable assertion-based checkers reduce the effort needed to verify complex Devices and interface protocols.

Use functional coverage metrics to direct the verification effort and measure progress.

Maximum use of random stimulus.

Creation and use of reusable verification components.

Portability across various levels of abstraction of the DUT.

Portability from block-level to system-level.

The VIP provides a fast, accurate way to simplify and speed-up the device verification task in a complex design process, verification can take up to 70% of the development time.

USB OTG Vera RVM VIP speeds up the verification process providing a compelling cost and time to market. Object Oriented Programming approach plays one of the key roles to achieve these goals. Writing a reusable code makes it easy for the Verification Engineer to apply the same tasks in various modules from project-to-project and code is maintainable.

The VIP can work with 8-bit or 16-bit standard USB OTG Dual-Role devices.

Error Injection Mechanism, which can be turned ON or OFF for a given simulation run.

Incorporated around 50 scenarios for different Error types Provides a choice for RESETTING to either High-Speed or Full-Speed mode upon startup.

Supports RESET/SUSPEND/RESUME. On-the-fly Reset switch over from High-Speed to Full-Speed or vice-versa supported.

Synopsys RVM compliant

Absence of inter-module dependencies makes the VIP highly reusable

Programmable and Randomized Transfer Types, namely INTERRUPT, ISOCHRONOUS, BULK and CONTROL

Hierarchical Seed Randomization.

Fully Constraints Driven Randomization of various fields of the Packets on both the interface ends of the IP

Initial DUT Health Checkup Mechanism

On-the-fly change in the role of the device from OTG A-Device to OTG B-Device or viceversa with Host Negotiation Protocol (HNP)

Support for Session Request Protocol (SRP) under Host functionality

Choice for inhibiting SUSPEND and / or RESET operation through use of simple macros

The product is bundled with a very fancy, intelligent and versatile Scoreboard that provides:

   • A bird’s eye view of the USB Transactions

   • Total number of Transactions and transfers with a split on successful / failure in various speeds and modes

   • Count of Token, Data and Handshake Packets sent / received

   • Status of transactions on supported / unsupported Device Addresses and Endpoint Adresses

   • Statistics on RESET / SUSPEND / RESUME activities

   • Error Injection statistics

   • Overall count of good / bad Packets

For a complete listing of features and pricing of SI70OTGRVM10, USB OTG Vera RVM VIP, please contact siliconcores@siliconinterfaces.com or visit the Silicon Cores web site at www.siliconcores.com

The SI70OTGRVM10, USB OTG Vera RVM VIP is available now.

USB OTG Vera RVM VIP can work in a standalone mode i.e. it can be plugged with any OTG Dual-Role Device with standard pin-outs without disturbing the structure of the front-end bus (UTMI+).