Why should I attend ?

From the United States to Japan, the word is out that incorporating Power Architecture either is in conjunction with or in sequence to Functional Verification using different languages, many times with different team members using different tools, and divergent approaches lead to potential errors, almost a fourth dimension to our strategy leveraging the test bench architecture. Industry seems to be following a parallel path with respect to Methodologies based test bench and Power Architecture, including Unified Power Formats (UPF). Both are fundamental requirements to IP and ASIC verification especially in the power saving mobile world. It would be more efficient to do Methodologies based Functional Verification and Coverage interleaved with Low Power Implementation. Join in to find out how!

Who should attend?

If you are a Design/Verification Engineer Professional working in Low Power Architecture with ASIC and SOC and interested in cutting short time to market guidelines by an uniform approach to Verification and Power then you will benefit with a step-by-step walk thru (with PCIe Phy as an example DUT) on how Low Power Classes as extension to UVM Package Library is changing the verification environment.

What are the details of the program?

1. Power Reduction Techniques
2. Power Management Architecture
3. Briefly explain UPF
4. Brief discussion on UVM Methodology
5. Incorporating UPF constructs within UVM
6. Extension to multiCore

Key takeaways from the Presentation and Demo.

Underlying thoughts are that a presentation and slides do not necessarily convey the information and an interactive practical walk-thru demo will implant knowledge more effectively. Also, the demonstration illustrates the service skills required and displays the capability matrix as well as the features Low Power Classes as extension to UVM Package Library. So, if you need a partner in your path to Low Power verification you will access to resources and tools under the same roof.